Fiche publication
Date publication
août 2021
Journal
ACS nano
Auteurs
Membres identifiés du Cancéropôle Est :
Dr DUJARDIN Erik
Tous les auteurs :
Kumar U, Cuche A, Girard C, Viarbitskaya S, Dell'Ova F, Al Rafrafin R, Colas des Francs G, Bolisetty S, Mezzenga R, Bouhelier A, Dujardin E
Lien Pubmed
Résumé
Processing information with conventional integrated circuits remains beset by the interconnect bottleneck: circuits made of smaller active devices need longer and narrower interconnects, which have become the prime source of power dissipation and clock rate saturation. Optical interchip communication provides a fast and energy-saving option that still misses a generic on-chip optical information processing by interconnect-free and reconfigurable Boolean arithmetic logic units (ALU). Considering metal plasmons as a platform with dual optical and electronic compatibilities, we forge interconnect-free, ultracompact plasmonic Boolean logic gates and reconfigure them, at will, into computing ALU without any redesign nor cascaded circuitry. We tailor the plasmon mode landscape of a single 2.6 μm planar gold cavity and demonstrate the operation and facile reconfiguration of all 2-input logic gates. The potential for higher complexity of the same logic unit is shown by a multi-input excitation and a phase control to realize an arithmetic 2-bit adder.
Mots clés
cavity modes, half-adder, logic gates, nonlinear photoluminescence, plasmonics, reconfigurable device
Référence
ACS Nano. 2021 08 24;15(8):13351-13359
